The present invention relates to a semiconductor device fabrication method, more specifically a semiconductor device fabrication method which can improve the inspection efficiency.
When semiconductor chips are completed on a semiconductor wafer, the inspection is made for confirming whether or not the semiconductor chips normally operate. Such inspection is called a probe test. The probe test is made by connecting to the bonding pads of the semiconductor chips with the probe needle which is connected to a semiconductor inspection equipment.
The probe test has been made on all the semiconductor chips so as to prevent the yield decrease in the final test made after semiconductor devices have been fabricated.
Recently, large-diameter semiconductor wafers of 8–12 inch-diameters are becoming dominant. When relatively small semiconductor chips of, e.g., about 2.5 mm×2,5 mm are fabricated on such large-diameter semiconductor wafer, 5000 or more semiconductor chips are fabricated on one sheet of semiconductor wafer.
When a period of time for the probe test per one chip is 3 seconds, about 4.1 hours are required to inspect one sheet of semiconductor wafer. For 1 lot of 25 sheets of semiconductor wafers, 4.3 days are required to inspect the semiconductor wafers of 1 lot.
To realize the cost reduction of semiconductor devices, it is very important to shorten the time required for the probe test.
Patent References 1 and 2 propose methods for shortening the time required for the probe test.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 10-242224/1998
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Sho 61-237443/1986
However, the methods described in Patent References 1 and 2 have not been able to drastically shorten the time required for the probe test.